Field
This disclosure relates generally to electronic circuits and more specifically to a duty cycle correction circuit having bounds on duty cycle deviation.
Related Art
A duty cycle is a percentage of a period of an active, or periodic, signal.
Commonly, it is desired that the duty cycle of a clock signal is 50 percent. A duty cycle corrector receives an input clock signal having a duty cycle different from desired and generates a clock signal having the same frequency but with a duty cycle closer to the desired duty cycle, for example, 50 percent. One duty cycle corrector includes a delay line having a plurality of series-connected current-starved inverters that function as the delay cells, and a differential operational amplifier based low-pass filter in a feedback loop from an output of a last inverter in the series to a first inverter. A current-starved inverter has an inverter with a current source and a current sink for controlling the current to the inverter from a power supply in response to a bias voltage. The bias voltage is provided by the low pass filter. If the supply voltage is reduced, such as in a low power operating mode, the current sourcing and sinking transistors of the delay cells turn off too much, which can completely shut off current source and/or current sink of the current-starved inverter, causing clock pulses to be skipped. The problem of skipped pulses is sometimes referred to as pulse swallowing. The skipped pulses will result in a corrupted output clock signal.
FIG. 1 illustrates, in schematic diagram form, duty cycle correction circuit 8 in accordance with the prior art. Duty cycle correction circuit 8 includes delay line 11, low pass filter 14, buffers 58 and 60, and inverter 62. Delay line 11 includes current-starved inverters 17, 19, and 21, and inverters 32, 44, and 56. Low pass filter 14 includes operational amplifier 64, resistors 66 and 68, and capacitors 70 and 72 and has differential inputs connected to the output of duty cycle correction circuit 8, and a single-ended output connected to each of the current source and current sink transistors of the delay line 11. In delay line 11, the current-starved inverters are connected in series with simple two-transistor inverters, where one two-transistor inverter follows each current-starved inverter. Each of the current-starved inverters is provided with a feedback bias voltage VBIAS from the output of low pass filter 14. The feedback bias voltage VBIAS controls the amount of delay for each pulse so that the output clock signal labeled “CLK OUT” has a 50 percent duty cycle. However, if bias voltage VBIAS skews too close to power supply voltage VDD, or to ground VSS because of a highly skewed input clock duty cycle, or if the power supply voltage drops too low, the current-starved inverters may fail to transition from one state to another. In FIG. 2, an input clock signal labeled “CLK IN” has a duty cycle different from 50 percent. One clock period of input clock signal CLK IN starts at time t0 and ends at time t2. Four clock periods are illustrated between time t0 and time t8. An output clock signal should have the same frequency with a duty cycle of 50 percent. FIG. 2 illustrates skipped inverter transitions so that some of the clock cycles are skipped because one or more of the inverters lacked sufficient current to transition. The corrupted output clock may cause data errors and/or a system malfunction.
Therefore, a need exists for a duty cycle correction circuit that solves the above problems.